Corel Netwinder Memory Map
| Address | Name | Width | Meaning |
| | | b[8] | IDE |
| | | b[4] | DMA base and current address (4 channels) |
| | | b[4] | DMA base and current count (4 channels) |
| | | b (write) | DMA command |
| | | b (read) | DMA status |
| | | b (write) | DMA control |
| | | b (write) | DMA mask register |
| | | b (write) | DMA mode register |
| | | b (write) | clear the toggle address bit for |
| | | b (write) | DMA hardware reset |
| | | b (write) | DMA clear all mask bits |
| | | b (write) | DMA set maks bits |
| | | b | DMA page registers |
| | | b | DMA extended mode |
| | ICW1 | b (write) (first write) | Irq Controller command (ICW1) |
| | OCW2 | b (write) (same addr) | Irq controller command (OCW2) |
| | OCW2 | b (write) (same addr) | Irq controller command (OCW2) |
| | ICW2 | b (write) | Irq init command (ICW2) |
| | ICW3 | b (write) (same addr) | Irq init command (ICW3) |
| | ICW4 | b (write) (same addr) | Irq init command (ICW4) |
| | OCW1 | b (write) (same addr) | Irq control reg (OCW1) (all further writes) |
| | | b (write) | Irq edge/level control |
Timers
| Address | Name | Width | Meaning |
| | | b (read twice) | Counter values |
| | | b (read back) | Counter status |
| | | b (write) | Counter control (common to all three) |
| | | s | Bios timer |
Misc
| Address | Width | Meaning |
| this looks incorrect! | b | NMI status/control |
| | b | RTC address |
| | b | RTC data |
| | b (write) | RTC CMOS RAM Proect 1 |
| | b (write) | RTC CMOS RAM Protect 2 |
| Address | Name | Width | Meaning |
| | | b | Parallel port data |
| | | b (read) | Parallel port print status |
| | | b (write) | Parallel port control |
| | | b (read) | Parallel port control swapper |
| | | b | EPP address port |
| | | b[4] | EPP dataports 0-3 |
| | BLL/BHL | b | UART divisor register; ! counts down from 24 MHz ! |
| | RBR/TBR | b | UART data reg: reads the rx byte, writes the tx byte |
| | ICR | b | UART Irq control |
| | ISR | b (read) | UART Irq status |
| | UFR | b (write) | UART Fifo control |
| | UCR | b | UART control reg |
| | HCR | b | UART handshake control |
| | USR | b | UART status reg |
| | HSR | b | UART handshake status |
| | UDR | b | UART user register |
| | | b | Super IO config register |
| | | b | ext-config-register data |
Misc IO
Several IO points are accessed through the "general purpose" pins on the superIO chip. We have programmed these registers to be at 0x330-0x
| Physical Address | Virtual Address | Width | Meaning |
| | E000.0330 (io: 330) | 16b | Misc IO registers |
| | | | |
| | 338 | b write | 0x80=turns on the red power LED |
| | 338 | b read | 1=do-it button is pushed |
| | | b | 1=copy data from serial register to output pins: set to 1, then set to 0 |
The "serial register" mentioned above is an external 4 bit register which holds:
first-shifted-bit=reset the termerature chip
second-shifted-bit=enable the mono speaker (0 to mute the speaker)
third-shifted-bit=enable flash write
last-shifted-bit=turn on front panel green LED
Ext-config-register
| Register (at | Width | Data (at |
| 2 | b | CR02 |
| 7 | b | CR07 |
| 20 | b (read) | CR20 device id |
| 21 | b (read) | CR21 rev |
| 22 | b | CR22 section power down |
| 23 | b | CR23 auto-power-down |
| 24 | b | CR24 PnP modes |
| 25 | b | CR25 |
| 26 | b | CR26 |
| 28 | b | CR28 |
| 29 | b | CR29 |
| | b | CR |
| 2B | b | CR2B more option pin assignments |
| | b | CR |
| 30 | b | CR30 section enable |
| 31 | b | CR31 |
| 60, 61 | b | CR60, CR61 address |
| 70 | b | CR70 interrupt control |
| 71 | b | CR71 interrupt control |
| 74 | b | CR74 DMA select |
| F0 | b | CRF0 clock select |
RTC data reg's
| Register (at | Width | Data (at |
| 0-9 | b[10] | RTC (bank 0) |
| A | b | RTC control (bank 0) |
| B | b | RTC control (bank 0) |
| C | b | RTC status (bank 0) |
| D | b | RTC status (bank 0) |
| E | b[72] | RTC user ram (bank 0) |
| 80-F7 | b | see W83977AF manual |
Super IO (cont'd)
The SuperIO contains a separate microprocessor controlling the keyboard and mouse. Communications to/from it are through this narrow portal....
| Virtual Address | Width | Meaning |
| e000.0060 | b | Keyboard controller |
| e000.0064 | b(write) | Keyboard command |
| e000.0064 | b(read) | Keyboard status |
Sound
There are many "mixer" type functions which can be programmed in the sound chip; please refer to the data sheet.
| Virtual Address | Width | Meaning |
| E000.0250 (io: 250) | 16b | Wave Artist sound device |
| 250 | b | command register |
| 251 | b read | 0x20=phone present & offhook |
| 251 | b write | init joystick timer |
| 252 | b | data register |
| 254 | b | control register |
| 255 | b | status register |
| | b | interrupt status |
This is a NE2000 clone, with some extensions in Bank3.
| Virtual Address | Width | Meaning |
| e000.0300 | b | command register |
| Bank 0 | ||
| e000.0301 | b (read) | DMA address lo |
| e000.0301 | b (write) | page start |
| e000.0302 | b (read) | DMA address hi |
| e000.0302 | b (write) | page end |
| e000.0303 | b | boundary pointer |
| e000.0304 | b (read) | tx status |
| e000.0304 | b (write) | tx page start |
| e000.0305 | b (read) | collision count |
| e000.0305 | b (write) | tx byte count lo |
| e000.0306 | b (read) | FIFO data |
| e000.0306 | b (write) | tx byte count hi |
| e000.0307 | b | irq status |
| e000.0308 | b (read) | DMA address lo |
| e000.0308 | b (write) | remote start address lo |
| e000.0309 | b (read) | DMA address hi |
| e000.0309 | b (write) | remote start address hi |
| e | b (write) | remote byte count lo |
| e000.030B | b (write) | remote byte count hi |
| e | b (read) | rx status |
| e | b (write) | rx config |
| e000.030D | b (read) | frame align error count |
| e000.030D | b (write) | tx config |
| e000.030E | b (read) | crc error count |
| e000.030E | b (write) | data config register |
| e | b (read) | missed packet error count |
| e | b (write) | irq mask |
| Bank 1 | ||
| e000.0301-6 | b[5] | physical address |
| e000.0307 | b | current page |
| e000.0308-F | b[8] | multicast address |
| Bank 2 | ||
| e000.0301 | b (read) | page start |
| e000.0301 | b (write) | current DMA addr 0 |
| e000.0302 | b (read) | page stop |
| e000.0302 | b (write) | current DMA addr 1 |
| e000.0303 | b | remote next packet pointer |
| e000.0304 | b (read) | tx page start address |
| e000.0305 | b | local next packet pointer |
| e000.0306 | b | address counter hi |
| e000.0307 | b | address counter lo |
| e | b (read) | rx config |
| e000.030D | b | tx config |
| e000.030E | b (read) | data config |
| e | b (read) | irq mask |
| Bank 3 | ||
| e | b | hardware config register |
| all banks | ||
| e000.0310-7 | b[8] | data buffer (nominally "remote DMA") |
| e000.0318 | b (read) | resets the Ether10 chip |
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